msxbuild/src/example/vhdl-chain/z80_bus_package.vhdl
Willem 7d7b134744
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Added some example for todo ghdl tooling flow support
2025-05-05 11:20:37 +02:00

113 lines
3 KiB
VHDL

library ieee;
use ieee.std_logic_1164.all;
package z80_bus_package is
constant FINAL_Z80_BUS_DATA_WIDTH : integer := 8;
constant FINAL_Z80_BUS_ADDRESS_WIDTH : integer := 16;
subtype stl_logic_z80_bus_addr is std_logic_vector(FINAL_Z80_BUS_ADDRESS_WIDTH-1 downto 0);
subtype stl_logic_z80_bus_data is std_logic_vector(FINAL_Z80_BUS_DATA_WIDTH-1 downto 0);
-- tri-state: cmd + addr + data see: z80_bus_master_phy_package
type stl_logic_z80_bus_cmd is record
mreq_n : std_logic;
iorq_n : std_logic;
rd_n : std_logic;
wr_n : std_logic;
end record stl_logic_z80_bus_cmd;
type stl_logic_z80_bus_cycle is record
m1_n : std_logic;
rfsh_n : std_logic;
halt_n : std_logic;
busack_n : std_logic;
end record stl_logic_z80_bus_cycle;
type stl_logic_z80_bus_sync is record
wait_n : std_logic;
int_n : std_logic;
nmi_n : std_logic;
busreq_n : std_logic;
rst_n : std_logic;
clk : std_logic;
end record stl_logic_z80_bus_sync;
type stl_logic_z80_ctl_sync is record
rst : std_logic;
clk : std_logic;
end record stl_logic_z80_ctl_sync;
type stl_logic_z80_ctl_cmd is (
CTL_IDLE,
CTL_MEM_READ_M1,
CTL_MEM_READ,
CTL_MEM_WRITE,
CTL_IO_READ,
CTL_IO_WRITE,
CTL_HALT
);
type stl_logic_z80_bus_master is record
cycle : stl_logic_z80_bus_cycle;
cmd : stl_logic_z80_bus_cmd;
data : stl_logic_z80_bus_data;
addr : stl_logic_z80_bus_addr;
end record stl_logic_z80_bus_master;
type stl_logic_z80_bus_slave is record
sync : stl_logic_z80_bus_sync;
data : stl_logic_z80_bus_data;
end record stl_logic_z80_bus_slave;
type stl_logic_z80_ctl_master is record
cmd_rfsh : std_logic;
cmd_req : std_logic;
cmd : stl_logic_z80_ctl_cmd;
data : stl_logic_z80_bus_data;
addr : stl_logic_z80_bus_addr;
end record stl_logic_z80_ctl_master;
type stl_logic_z80_ctl_slave is record
sync : stl_logic_z80_ctl_sync;
req_int : std_logic;
req_nmi : std_logic;
cmd_rdy : std_logic;
data : stl_logic_z80_bus_data;
end record stl_logic_z80_ctl_slave;
type stl_logic_z80_bus_state is (
BUS_IDLE,
BUS_MEM_T1,
BUS_MEM_T2,
BUS_MEM_TW,
BUS_MEM_T3,
BUS_MEM_RFSH,
BUS_MEM_RFSH_DONE,
BUS_IO_T1,
BUS_IO_T2,
BUS_IO_TWA,
BUS_IO_TW,
BUS_IO_T3,
BUS_INTACK_T1,
BUS_INTACK_T2,
BUS_INTACK_TWA,
BUS_INTACK_TW,
BUS_INTACK_T3,
BUS_REQUEST_TLW,
BUS_REQUEST_TX,
BUS_REQUEST_DONE,
BUS_HALT,
BUS_RESET,
BUS_RESET_DONE
);
end z80_bus_package;