Added bereshit printer + zr8000 cpu

README-MSX4.md

@@ -36,7 +36,25 @@ By moving the MMU from the CPU to the system network we get "The Matrix";
 
 ![msx-mmu-1998](local-img/msx4/msx-mmu-1998.png "msx-mmu-1998")
 
-### CPU: TR808
+### CPU: ZR8000
+
+Intermediate upgraded cpu for embedded platform and edge nodes of msx4 system.
+
+- 100% z80 compatible + fast mode
+- 16 bit bus + new T16 I/O space
+- split program and data memory space
+- (nmi) int vector on SP value X and Y (software based infinity stack)
+
+Memory Typed Machine Structure (like cray-1)
+
+- 8,16,32,64,128 bit integer
+- 3,6,9,18,36,72 bit structure
+- 144 bit decimal
+- 144 bit(++) 7HFF number
+
+For example "MTADD (IX),(IY)" reads the type from memory not from instruction.
+
+### CPU: TR9000
 
 A bit pulsetrain clockless design is the goal for the beating heart.
 But in FPGA's there can be a more normal design.