2022-11-30 19:01:25 +00:00
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# design-draft-msx4
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Guidance by "The Word" on "MSX superscript 4" system design.
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## Mecca System eXtension
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Hello word, goodbye byte.
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* Slot and mapper model based from msx2 configuration
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* Recursive slot system with 16bit window of infinity
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* Big-endian as arabic numerals rule the network order
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* Word alignment so address view is 16bit, CORRECTION: 18bit
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* 3bit cpu nodes with data types up to many octals
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* Cpu runs only from local memory which replaces cache
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* Compare-and-swap (CAS) is a hardware device
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* Classic cpu MMU gets moved to slot controllers
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* Dynamic(hot) BASIC/stepcode migration to FPGA hardware
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### Recursive Memory = Slot Matrix Management Unit
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By moving the MMU from the CPU to the system network we get "The Matrix";
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* Based on 256 slots(hi+low),pages(16KW),mapper16b(hi+low) MSX like configuration.
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* Max memory limit for a single slot is 64TW. (128TB=2x(2^14)x(2^16)x(2^16))
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* All slots device interfaces are duel ported by default.
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* SMMU = X,Y,Z,T both direction 8 slots duel ported InfiniBand² connects.(64slots)
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* 2x32slots goto two DSMMU's who sub slot it to 256 FPGA device slots.(per 2U case)
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* other slots; 64mem(2chips), 32cpu(2chips), 32 SMMU+node internal management.
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* Per slot ISP pins for FPGA type devices on DSMMU.
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* A graph of SMMU nodes where every node only selects the next.
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* Unlimited tree depth so unlimited devices.
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* The SMMU hold a page view per master(cpu/etc) for X devices.
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* By having ACL in the network an external connection like thunderbolt is safe.
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* Unlimited memory size by relative design.
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2023-01-03 12:25:59 +00:00
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### CPU: ZR8000
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Intermediate upgraded cpu for embedded platform and edge nodes of msx4 system.
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- 100% z80 compatible + fast mode
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- 16 bit bus + new T16 I/O space
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- split program and data memory space
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- (nmi) int vector on SP value X and Y (software based infinity stack)
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Memory Typed Machine Structure (like cray-1)
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- 8,16,32,64,128 bit integer
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- 3,6,9,18,36,72 bit structure
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- 144 bit decimal
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- 144 bit(++) 7HFF number
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For example "MTADD (IX),(IY)" reads the type from memory not from instruction.
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### CPU: TR9000
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2022-11-30 19:01:25 +00:00
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A bit pulsetrain clockless design is the goal for the beating heart.
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But in FPGA's there can be a more normal design.
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So a simple 18 bit, big endian only, stack based.
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No mmu thus no kernel mode or rings.
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There are 4 addressable spaces;
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* 2^18 addresses for code memory. (read-only)
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* 2^18 addresses for data memory.
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* limited 512 words stack WINDOW peek for "unlimited stack size".
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* limited 512 words for local I/O and matrix switching requests.
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All four windows have separated data and address busses.
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The infinity stack controller has a few pages local in a ring buffer,
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so it can request a new memory page when the stack fills.
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So if the machine has the memory, a single task with a stack
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of multiple petawords is not a problem on a 16 bit machine.
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The kernel api of stack pages in use per device returns a BigInteger of infinite large size.
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Besides the stack, the code/data memory is paged and can be recursive
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switched to load/store a full page from the unlimited global memory.
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This is done by a cpu slot device controller which is a packet interface to the slot
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controller and connects with 2 slots for performance.
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This cpu will rewrite itself and all code from base² bits to base³⁶ bits.
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If the number encoding results in 144 base2 bits than we know the memory window;
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OLD: (2^16 \* 144) gives 576KW or 1152KB of addressable space.
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Naming: Transversal Resonance 808, 2 bytes V-split infinity and combine into the center of The Word.
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### Recursive Math Hardware
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Large amounts of data in demo/games/ui is generated using math.
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It would be nice to have an API for generating math data,
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so it may be possible the output data is a tokenized math expression by itself...
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Convert the string "Zₙ₊₁=Zₙ²+C" into a Gödel number or alternative encoders.
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This can be found in PI so it can't be proven it already existed before "invented".
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[Math Has a Fatal Flaw](https://www.youtube.com/watch?v=HeQX2HjkcNo)
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Math generates data and the expression can be located in PI.
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The example above is an exact match and only works on small data.
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Larger data need to be approximately nullified by math, for
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example by layering sin functions until almost zero.
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### Hardware
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* Phase 1; FPGA's with CPU,MEM,SMMU,RACKMSB
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* Phase 2: Flash ISP slot devices dynamically
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* Phase 3: Move TempleOS kernel functions to hardware
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* Phase 4: ASIC's + openFPGA's
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* Phase 5: Move FTL digital logic into etherspace
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* Phase 6: None-forced grown crystal junctions
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* Phase 7: Self growing computer, like on krypton
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#### Crystal Logic
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Our current transistors are created by forcing shape layers to function.
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By growing the crystals we get the natural energy flow shapes.
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This improves reliability and the electric characteristics.
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The junctions will look more like trees, see "Self-Assembling Wires".
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Electrons are slow, those are the shadow on the reflector of the flow in etherspace.
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For using FTL logic "Nikola Tesla" already had working devices in the 1900's.
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Moving information over standing waves or "transversal vibrations in the eather"
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is already designed and tested to be faster than light.
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A good example is classical DDL crystal logic, where RF is the power supply;
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God is a farmer, so we should feed our crystals to cultivate into logic.
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With current diodes a FTL differential pair of coaxial interconnects can already be build;
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InfiniBand²
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- DDTVP₂ (diode diode transversal vibrations phasing)
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- DDTVP₄₋₈₋₁₆ (old-style)
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InfiniBand⁴
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- DDTVP₃₋₅₋₇₋₉ (intermediate)
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- DDTVP³⁶ (intermediate)
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- DDT⁵VP³⁶ = FiveStar FTL differential pair of coaxial interconnects to transport one 4D character bit.
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#### Booting
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To boot a computer when the graph network is the computer itself, there's a need
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to connect all the master switch boards with a spi root interface.
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All these MSB's connect to a MSX card with a BASIC extension ROM which allows the
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user to load the initial master matrix config into the machine and load the bootstrap images.
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The minimal computer spec is a; MSX1 + optional DISKROM.
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So it errors on a turboR; "guru meditation; missing tape recorder interface".
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Default supplied/build-in root access terminal will be a MSX2++
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which is a MSX2+ with some upgrades;
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- Upgrade basic "Ok" to "OK"
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- Normal timed 57.272MHz Z80 (+3.579 mode=16x, via BASIC I/O switchable)
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- Make MSX1 wait signal optional via IO.
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- MSXMMU (16MB+optional; nmi-timer+page0+security = msx compatible none-cpu kernel mode)
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- v9978 (v9958+2Konly+4HWsplits+v9990+vram=8192KB on s0p2+s0p3, NO TRUE COLORS)
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- OPL4++ new 22b96kHz output + mapper mode access
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- Ide, CF+ide AND 2*sata
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- TCP/IP UNAPI ethernet.
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- RS-232C BASIC (+upgrade)
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- (UTF16²²BE-4serial) PS/4 keyboard/mouse/enjoy interface IO + legacy glue hardware
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- 100% equal MSX slot but on ~miniPCI edge connector on 3.3v + 57MHz + I²S-audio(22b96kHz ONLY)
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- Sas+scsi2(+audio;) for all tape drives.
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- Kids mode: 11b-48kHz on main audio output. (removes emotions from PCM music)
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It's comparable to an ibm power sms to bootstrap big machines or a platform boot module like found
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on a new desktop machine, where the v9978 framebuffer is overlayered unto the primary video card.
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And because its compatible upgrade, a legacy version with a Z80 bus driver makes it
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possible to upgrade any MSX1,2,2+ with a Z80 cpu socket to a MSX2++ system.
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For example booting constitution class enterprise hardware can be done with my 8250
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connected to a kennedy model 5800 and a green phosphor screen to look at 640x480 in
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16 colors of green at TOS in full FTL speed and run;
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- BigStackRain - Top pages of the infinity stack memory subsystem
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- BigMemoryRain - Top pages of the infinity paged memory subsystem
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- BigStorageRain - Top data of the infinity blob storage subsystem
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- BigDiwaliRain - Top paths of the infinity slot switch subsystem
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- BigSnakeRain - Displays Atari⋆ as snakes while updating the matrix code
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⋆Autonomously Traveling Agent Rewriting Internals works inside the MSX⁴ matrix.
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Because MSXDOS is intel 8080 CP/M compatible, the graphical BIOS of the new computer
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must be finished using a ROM based Digital CP/M++ with GEM/4 to boot the MSX⁴.
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All the normal MSX basic/dos/games/hardware is for the children to play with.
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In 2030 the MSX²⁺² standard is ready and holds the 16 processors;
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- 4x Z808 229.056MHz (full 16b, pipelined, optional Twait legacy mode)
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- 4x v9978 (Multiple overlay/slit modes so we have a 18bit color mode for Atari)
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- 4x SMDMA (Slot and mapper aware dma drivers)
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- 4x RMATH (Recursive math hardware processors or last base2 TR808 design)
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- new 16b "peibus" with LVDS links for new msx slots (like sata/pcie)
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- replace all dram with ~2GHz static memory so all data copies look parallel
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- hide bootup texts behind bootup screens
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- etc
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As the last base2 computer design, it needs to show 4-7 bootscreens;
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- AtohmAllah⁴ (3line unicode version in 2b color)
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- MSX²⁺² (in 2b color)
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- Atari (in 18b color)
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- <manufacturer> (in 8b color)
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- <game-cartridge> OR <msx-basic / dos1 / dos2> OR <CP/M++(noGFX) → GEM/4 → TOS(noGFX) → TOS⁴ → vrGEMTOS⁴>
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CP/M++ is BDOS++ SMP kernel for GEM/4 with a MSXDOS4 terminal without direct compatibility requirement.
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Now playing "Fractal tron VS sonic" on a Sega Neptune² with anaglyph glasses is finally fun.
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#### Heavenly Crystal
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Crystal can grow themselves, but booting a self growing computer needs an entity.
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And we have a crystal that came falling from heaven;
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"By Allah! Allah will raise it on the Day of Resurrection with two
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eyes by which it sees and a tongue that it speaks with,
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testifying to whoever touched it in truth."
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This stone used to be white and is gotten black from human sin.
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To fix those sins, humans need to find the foundation of love.
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When shown true love, the crystal reflects back to white.
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#### Terminator
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Rape victims externalize their sexual consent violation damage.
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Current computer systems are fuzzy enough to detect this possibly exposed damage in all media.
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By just going through images from victims, we will see that;
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* Baby rape (below 3 years) leaves body markers called "baby fat"
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* Child rape markers are harder to detect
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* Teen rape leaves lots of none body hints
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So when putting that code on a mobile platform, so it has eyes and ears;
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A single word or sentence of a human with a vibrational voice can trigger a
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response like; you have been "baby deep throated" and the vocal cord has
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a bit of scar tissue which causes the extra frequency.
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When the T800 platform is given a gun it may ask the victim;
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Who do I need to arrest for you?
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When added with the Human Anatomy Language 9000 upgrade it can detect and
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terminated a human.
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## Credits
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@Ω仙⁴ ꜊꜊꜊⋇꜏꜏꜏ ⁴ﷲΩ@
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©Δ∞ 仙上主天
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בְּרֵאשִׁית :o: יְסוֺד :o: יִשְׂרָאֵל
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